Logic Gates

Definition: Logic gates are basic digital circuits that perform Boolean operations, like AND, OR, and NOT, on one or more binary inputs to produce a single output.

How It Works

Each gate follows a fixed truth table mapping every input combination (0s and 1s) to an output
Internally, gates are built from transistors wired as electronic switches: in CMOS logic, complementary pairs of NMOS and PMOS transistors pull the output high or low
A logic-level “1” (or HIGH) is a voltage near the supply rail; a “0” (or LOW) is a voltage near ground; the exact thresholds depend on the logic family (TTL, CMOS, etc.)
NAND and NOR gates are functionally complete, meaning any Boolean function, and therefore any digital circuit, can be built using only one of those gate types
Gates are combined into larger structures: adders, multiplexers, flip-flops, and ultimately entire processors
Propagation delay, the time between an input change and the corresponding output change, limits how fast a chain of gates can operate
Real gates draw a small amount of current even when idle (static power) and more during switching (dynamic power), both of which matter for battery-powered designs

Gate Types at a Glance

AND — outputs 1 only if all inputs are 1
OR — outputs 1 if at least one input is 1
NOT (inverter) — flips a single input
NAND — AND followed by NOT; universal gate
NOR — OR followed by NOT; universal gate
XOR — outputs 1 if inputs differ (odd number of 1s); used in adders
XNOR — outputs 1 if inputs match (even number of 1s); used in equality comparators
Buffer — outputs the same logic level as input, used to restore signal strength or add delay

Illustration

Under the Hood

Boolean expressions for the core gates:

AND:  Y = A · B
OR:   Y = A + B
NOT:  Y = A'
NAND: Y = (A · B)'
NOR:  Y = (A + B)'
XOR:  Y = A ⊕ B
XNOR: Y = (A ⊕ B)'

De Morgan’s Theorem, which shows why NAND/NOR are functionally complete:

(A · B)' = A' + B'
(A + B)' = A' · B'

Propagation delay budget for a chain of n gates:

T_total = n × t_pd

where t_pd is the propagation delay of a single gate.

Worked Problem 1: full truth table for a 2-input AND gate Given: inputs A and B, each either 0 or 1. Step 1: A=0, B=0 → Y = 0 · 0 = 0. Step 2: A=0, B=1 → Y = 0 · 1 = 0. Step 3: A=1, B=0 → Y = 1 · 0 = 0. Step 4: A=1, B=1 → Y = 1 · 1 = 1. Answer: AND outputs 1 only when both inputs are 1.

Worked Problem 2: full truth table for a 2-input XOR gate Given: inputs A and B. Step 1: A=0, B=0 → Y = 0 (inputs match). Step 2: A=0, B=1 → Y = 1 (inputs differ). Step 3: A=1, B=0 → Y = 1 (inputs differ). Step 4: A=1, B=1 → Y = 0 (inputs match). Answer: XOR outputs 1 only when the inputs differ, making it the basis of binary addition (sum bit).

Worked Problem 3: building AND from only NAND gates Given: only NAND gates are available, and AND is needed. Step 1: NAND(A, B) = (A · B)’. Step 2: Feed that NAND output into a second NAND gate as both inputs: NAND(X, X) = X’. Step 3: X’ = ((A · B)’)’ = A · B. Answer: two NAND gates in series (second one wired as an inverter) reproduce an AND gate, proving NAND alone is functionally complete.

Worked Problem 4: propagation delay through a chain Given: a signal passes through 5 gates in series, each with a propagation delay of 3 ns. Step 1: T_total = n × t_pd = 5 × 3 ns. Answer: T_total = 15 ns, meaning the maximum clock frequency this path could support is roughly 1 / 15ns ≈ 66.7 MHz before timing violations occur.

Quick Reference: All 2-Input Gate Outputs

A	B	AND	OR	XOR	NAND	NOR	XNOR
0	0	0	0	0	1	1	1
0	1	0	1	1	1	0	0
1	0	0	1	1	1	0	0
1	1	1	1	0	0	0	1

Why It Matters

Logic gates are the fundamental building blocks of all digital electronics, from simple counters to entire processors
Every microprocessor, no matter how advanced, is ultimately millions or billions of these same few gate types wired together
Understanding gate-level behavior is essential for digital design, debugging embedded systems, and understanding how software instructions become physical switching events
Gate propagation delay directly limits the maximum clock speed a digital system can reliably run at

Common Pitfalls

Confusing OR with XOR: OR outputs 1 when either or both inputs are 1, XOR only when exactly one input is 1
Leaving unused digital inputs floating instead of tying them to a defined HIGH or LOW, letting noise randomly flip the gate’s output
Forgetting propagation delay: a gate’s output doesn’t change instantaneously, which matters when chaining many gates in a timing-critical path
Mixing logic families (e.g., driving a 5V TTL input with a 3.3V CMOS output) without checking voltage compatibility, leading to unreliable HIGH detection
Assuming a NOT gate and an inverter buffer are interchangeable in all cases; some “inverting buffers” have different drive strength or timing than a simple logical NOT
Overloading a gate’s fan-out, driving more downstream gates than its output can reliably supply current to
Creating unintended combinational loops (feedback without proper latch/flip-flop design), causing oscillation or unpredictable states
Ignoring setup and hold time requirements when gate outputs feed into clocked flip-flops

Comparison

Gate	Output is 1 when…	Functionally Complete?	Typical Symbol Shape
AND	All inputs are 1	No	D-shaped
OR	At least one input is 1	No	Curved shield shape
XOR	Exactly one input is 1 (odd number of 1s)	No	Curved shield with extra line
NAND	Not all inputs are 1	Yes	D-shape with bubble
NOR	No inputs are 1	Yes	Curved shield with bubble
XNOR	Inputs match (even number of 1s)	No	Curved shield with extra line and bubble

History

Boolean algebra, the mathematical basis for logic gates, was developed by George Boole in 1854 as a system of symbolic logic
Claude Shannon’s 1937 master’s thesis showed that Boolean algebra could describe and design electrical switching circuits, directly enabling digital circuit design
Early logic gates were built from relays, then vacuum tubes, then discrete transistors, before being integrated onto single chips in the 1960s
The 7400 series of TTL logic ICs, introduced by Texas Instruments in 1964, became a standard building block for digital circuits for decades
CMOS logic, developed in the late 1960s and dominant since the 1980s, largely replaced TTL because of its far lower static power consumption

Example

A car’s ignition safety circuit uses an AND gate: the starter motor engages only when both the key is turned AND the brake pedal is pressed, so either input alone leaves the output LOW and the starter off. The 7400 quad NAND gate IC, still manufactured today, is a classic example students use to build simple logic circuits on a breadboard.

FAQ

Why are NAND and NOR called “universal gates”? Because any Boolean function, including AND, OR, and NOT themselves, can be constructed using only NAND gates or only NOR gates, which simplifies IC manufacturing to a single gate type.

What’s the difference between combinational and sequential logic? Combinational logic (built from gates alone) has outputs that depend only on current inputs; sequential logic adds memory elements like flip-flops so outputs also depend on past state.

Can logic gates have more than two inputs? Yes, AND, OR, NAND, and NOR gates commonly come in 3-, 4-, or 8-input versions; the same Boolean rule just extends to all inputs.

Why does real hardware use NAND gates internally even for a chip labeled “AND”? CMOS NAND gates are naturally faster and use fewer transistors than CMOS AND gates, so an “AND” IC is often just a NAND gate followed by an inverter.

What is fan-out, and why does it matter? Fan-out is the number of gate inputs a single gate’s output can reliably drive; exceeding it starves downstream gates of enough current to register a valid logic level.

Do logic gates exist as standalone components anymore, or only inside larger chips? Both: standalone gate ICs (like the 7400 series) are still sold for glue logic and education, but the vast majority of gates today exist as tiny structures inside larger ASICs, FPGAs, and microcontrollers.

Referenced by

Dig deeper

Spot an error in this note?